Vertically-integrated VLSI Information Processing


Vertically-integrated VLSI Information Processing

VVIP Lab Opening

VVIP Lab is looking for highly-motivated students for Ph.D and master programs.

Currently, we are looking for three research pillars listed below, and the required skillsets as an ideal candidate are also described for each pillar:

1. Digital machine learning accelerator architecture:

  - Verilog/VHDL, synthesis/auto-PnR with Cadence tools

2. Mixed-signal circuit for low-power AI hardware:

  - Full custum transistor-level circuit design, silicon tape-out experience highly welcomed

3. Algorithm hardware co-optimization in machine learning system:

  - Pytorch/tensor flow, familar with machine learning network models for inference/training


Though you choose specific pillar, every student will be trained for all three pillars during their Ph.D program. Please see my teaching philsophy by clicking here.

If you are interested in applying VVIP Lab, please fill out my name during your application process for UCSD ECE department or state your interest in your statement of purpose.


For any further questions, you can email me: m7kang@ucsd.edu. For better understanding, please follow the guidline below:

- State which pillar (out of three pillars listed above) you are interested in.

- State which program you are interested in. (e.g., Ph.D / MS)

- Attach your updated CV, TOFLE/GRE score, and transcript (optional) 

- Please do not send an email multiple times unless you have an update in your CV (e.g., new publication / award / or other significant achievement)

- Please send a remind email in January 2021

- I appologize that I might not be able to reply due to high volume of emails. But, I am checking emails for sure, and keeping track of potential applicants with great fit.


UCSD Electrical and Computer Engineering (ECE) Department