This course provides "hands-on" VLSI design guideline of the machine learning (ML) accelerator architectures across top-to-down vertical layers including algorithm, architecture, and circuit. The overview/theory of training and inference of deep neural network and other ML algorithms are provided. Students are supposed to train and validate their own network models for computer vision and natural language processing (NLP) applications via python (pytorch) programming. Then, the network model is mapped on the hardware by applying multiple low-power techniques including quantization, pruning, compression, and sparsity-aware circuit techniques. Students design their own architecture with verilog programming and verify the functionality with their test benches from python. Finally, the design is synthesized and evaluated with the Quartus Prime for FPGA emulations.
- Recommended preparation: ECE111 or equivalent course (which covers verilog & digital logic design).
- Prior knowledge of Machine learning is not required to take this course.